Fixing some naive assumptions, making shell for parsing an instruction from memory.

src/cpu.zig

@@ -15,8 +15,8 @@
 // along with this program. If not, see <https://www.gnu.org/licenses/>.
 
 const std = @import("std");
-const mem = @import("memory.zig");
-
+const instructions = @import("instructions.zig");
+const memory = @import("memory.zig");
 pub const Register = enum {
     EAX,
     EBX,
@@ -52,4 +52,54 @@ pub const Cpu = struct {
                 .initFill(0x00000000),
         };
     }
+
+    pub fn executeInstruction(
+        self: *Cpu,
+        mem: *memory.Memory,
+        instruction: instructions.Instruction,
+    ) !void {
+        _ = mem;
+        _ = self;
+        switch (instruction.opcode) {
+            instructions.Opcode.MovRegToRegMem_8 => {},
+        }
+    }
+
+    fn makeInstruction(
+        self: *Cpu,
+        mem: *memory.Memory,
+    ) instructions.Instruction {
+        const modrm: ?u8 = null;
+        const sib: ?u8 = null;
+        const displacement: ?u8 = null;
+        const immediate: ?u8 = null;
+        const prefix = self.parsePrefix(&mem);
+        const opcode = mem.readByte(self.instruction_pointer);
+        self.instruction_pointer += 1;
+        if (instructions.opcodeRequiresModRM(opcode)) {
+            modrm = mem.readByte(self.instruction_pointer);
+            self.instruction_pointer += 1;
+            //TODO: SIB
+            //TODO: Displacement
+        }
+        if (instructions.opcodeRequiresImmediate(opcode)) {
+            //TODO: Handle immediates
+        }
+        return instructions.Instruction{
+            .prefix = prefix,
+            .opcode = opcode,
+            .modrm = modrm,
+            .sib = sib,
+            .displacement = displacement,
+            .immediate = immediate,
+        };
+    }
+
+    fn parsePrefix(
+        self: *Cpu,
+        mem: *memory.Memory,
+    ) instructions.Prefix {
+        _ = self;
+        _ = mem;
+    }
 };

src/instructions.zig

@@ -33,7 +33,7 @@ pub const Prefix = struct {
 
 pub const Instruction = struct {
     prefix: Prefix,
-    opcode: u8,
+    opcode: Opcode,
     ///The MOD-REG-R/M byte specifies instruction operands and their addressing mode.
     modrm: ?u8 = null,
     ///Scaled indexed addressing mode uses the second byte (namely, SIB byte)
@@ -43,7 +43,7 @@ pub const Instruction = struct {
     immediate: ?u8 = null,
 };
 
-pub const Opcode = enum {
+pub const Opcode = enum(u8) {
     //
     MovRegToRegMem_8 = 0x88,
     MovRegToRegMem_16_32 = 0x89,
@@ -59,3 +59,13 @@ pub const Opcode = enum {
     //
     MultiByte = 0xFF,
 };
+
+pub fn opcodeRequiresModRM(opcode: Opcode) bool {
+    _ = opcode;
+    return false;
+}
+
+pub fn opcodeRequiresImmediate(opcode: Opcode) bool {
+    _ = opcode;
+    return false;
+}

src/main.zig

@@ -42,6 +42,7 @@ const SEGMENT_REGISTER_USAGE = SEGMENT_REGISTER_COMMAND;
 const HELP_USAGE = HELP_COMMAND;
 const CLEAR_USAGE = CLEAR_COMMAND;
 const EXIT_USAGE = EXIT_COMMAND;
+
 pub fn main() !void {
     var memory = mem.Memory.init();
     var cpu = cpu_.Cpu.init();

src/memory.zig

@@ -25,11 +25,11 @@ pub const Memory = struct {
         };
     }
 
-    pub fn readByte(self: *Memory, addr: u8) !u8 {
+    pub fn readByte(self: *Memory, addr: u32) !u8 {
         return self.data[addr];
     }
 
-    pub fn writeByte(self: *Memory, addr: u8, value: u8) !void {
+    pub fn writeByte(self: *Memory, addr: u32, value: u8) !void {
         self.data[addr] = value;
     }
 };