CPU and instruction declarations.
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24
src/cpu.zig
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24
src/cpu.zig
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const std = @import("std");
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const mem = @import("memory.zig");
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pub const Register = enum {
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EAX,
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ECX,
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EDX,
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EBX,
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//
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ESP,
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EBP,
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ESI,
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EDI,
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};
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const Opcode = enum {};
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pub const Cpu = struct {
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registers: std.EnumArray(Register, u32),
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instruction_pointer: u32, //EIP
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pub fn execute(self: *Cpu, memory: *mem.Memory, opcode: u8, reg1: Register, reg2: Register) void {
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switch (opcode) {}
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}
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};
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28
src/instructions.zig
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28
src/instructions.zig
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pub const Prefix = struct {
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///Prefix byte guarantees that instruction will have exclusive
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///use of all shared memory, until the instruction completes execution.
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lock: bool = false,
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///Repeats instruction the number of times specified by iteration count ECX.
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rep: bool = false,
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///Prefix causes memory access to use specified segment
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///instead of default segment designated for instruction operand.
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segmentOverride: u8,
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///Changes size of data expected by default mode of the
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///instruction e.g. 16-bit to 32-bit and vice versa.
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operandOverride: bool = false,
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///Changes size of address expected by the instruction.
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///32-bit address could switch to 16-bit and vice versa.
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addressOverride: bool = false,
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};
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pub const Instruction = struct {
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prefix: Prefix,
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opcode: u8,
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///The MOD-REG-R/M byte specifies instruction operands and their addressing mode.
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modrm: ?u8 = null,
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///Scaled indexed addressing mode uses the second byte (namely, SIB byte)
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///that follows the MOD-REG-R/M byte in the instruction format.
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sib: ?u8 = null,
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displacement: ?u8 = null,
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immediate: ?u8 = null,
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};
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