CPU and instruction declarations.

src/cpu.zig

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+const std = @import("std");
+const mem = @import("memory.zig");
+
+pub const Register = enum {
+    EAX,
+    ECX,
+    EDX,
+    EBX,
+    //
+    ESP,
+    EBP,
+    ESI,
+    EDI,
+};
+
+const Opcode = enum {};
+
+pub const Cpu = struct {
+    registers: std.EnumArray(Register, u32),
+    instruction_pointer: u32, //EIP
+    pub fn execute(self: *Cpu, memory: *mem.Memory, opcode: u8, reg1: Register, reg2: Register) void {
+        switch (opcode) {}
+    }
+};

src/instructions.zig

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+pub const Prefix = struct {
+    ///Prefix byte guarantees that instruction will have exclusive
+    ///use of all shared memory, until the instruction completes execution.
+    lock: bool = false,
+    ///Repeats instruction the number of times specified by iteration count ECX.
+    rep: bool = false,
+    ///Prefix causes memory access to use specified segment
+    ///instead of default segment designated for instruction operand.
+    segmentOverride: u8,
+    ///Changes size of data expected by default mode of the
+    ///instruction e.g. 16-bit to 32-bit and vice versa.
+    operandOverride: bool = false,
+    ///Changes size of address expected by the instruction.
+    ///32-bit address could switch to 16-bit and vice versa.
+    addressOverride: bool = false,
+};
+
+pub const Instruction = struct {
+    prefix: Prefix,
+    opcode: u8,
+    ///The MOD-REG-R/M byte specifies instruction operands and their addressing mode.
+    modrm: ?u8 = null,
+    ///Scaled indexed addressing mode uses the second byte (namely, SIB byte)
+    ///that follows the MOD-REG-R/M byte in the instruction format.
+    sib: ?u8 = null,
+    displacement: ?u8 = null,
+    immediate: ?u8 = null,
+};